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SI8430/31/35
TRIPLE- CHANNEL DIGITAL IS O L A T O R
Features
High-speed operation: DC - 150 Mbps Low propagation delay: <10 ns Wide Operating Supply Voltage: 2.375-5.5V Low power: I1 + I2 < 12 mA/channel at 100 Mbps Precise timing: 2 ns pulse width distortion 1 ns channel-channel matching 2 ns pulse width skew 2500 VRMS isolation Transient Immunity: >25 kV/s Tri-state outputs with ENABLE control DC correct No start-up initialization required <10 s Startup Time High temperature operation: 125 C at 100 Mbps 100 C at 150 Mbps Wide body SOIC-16 package Pin Assignments
Wide Body SOIC
VDD1 GND1 A1 A2 A3 NC EN1/NC GND1
1 2 3 4 5 6 7 8
Top View
16 15 14 13 12 11 10 9
VDD2 GND2 B1 B2 B3 NC EN2/NC GND2
Applications
Isolated switch mode supplies Isolated ADC, DAC Motor control Power factor correction systems
Safety Regulatory Approvals
UL recognition:2500 VRMS for 1 Minute per UL1577 CSA component acceptance notice VDE certification conformity
IEC 60747-5-2 (VDE0884 Part 2)
Description
Silicon Lab's family of digital isolators are CMOS devices that employ an RF coupler to transmit digital information across an isolation barrier. Very high speed operation at low power levels is achieved. These parts are available in a 16-pin wide body SOIC package. Three speed grade options (1, 10, 150 Mbps) are available and achieve typical propagation delay of less than 10 ns.
Block Diagram
SI8430/35 Si8431
A1 A2 A3 NC
B1 B2 B3 EN2/NC
A1 A2 A3 EN1
B1 B2 B3 EN2
Rev. 0.3 8/07
Copyright (c) 2007 by Silicon Laboratories
SI8430/31/35
SI8430/31/35
2
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SI8430/31/35 TABLE O F CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3. Enable (EN1, EN2) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . . 24 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
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1. Electrical Specifications
Table 1. Electrical Characteristics
(VDD1 = 5 V, VDD2 = 5 V, TA = -40 to 125 C)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Enable Input High Current Enable Input Low Current SI8430/35-A,-B,-C, VDD1 SI8430/35-A,-B,-C, VDD2 SI8430/35-A,-B,-C, VDD1 SI8430/35-A,-B,-C, VDD2 Si8431-A,-B,-C, VDD1 Si8431-A,-B,-C, VDD2 Si8431-A,-B,-C, VDD1 Si8431-A,-B,-C, VDD2 SI8430/35-B,-C, VDD1 SI8430/35-B,-C, VDD2 Si8431-B,-C, VDD1 Si8431-B,-C, VDD2 SI8430-C, VDD1 SI8430-C, VDD2 Si8431-C, VDD1 Si8431-C, VDD2
Symbol VIH VIL VOH VOL IL IENH IENL
Test Condition
Min 2.0 --
Typ -- -- 4.8 0.2 -- 4 20 7 6 14 6 8 10 13 12 11 13 12 13 11 23 13 21
Max -- 0.8 -- 0.4 10 -- -- 10 9 18 9 12 15 19 17 15 17 16 17 15 28 18 26
Unit V V V V A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
loh = -4 mA lol = 4 mA VENx = VIH VENx = VIL All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC
VDD1,VDD2 - 0.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DC Supply Current (All inputs 0 V or at Supply)
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
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Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = -40 to 125 C)
Parameter Si843x-A Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL|
Symbol
Test Condition Timing Characteristics
Min
Typ
Max
Unit
0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 -- -- -- -- 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 -- -- -- -- 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 4 -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- 6.5 -- -- --
1 1000 75 30 50 40 10 100 35 7.5 25 5 150 6.6 9.5 3 5.5 3
Mbps ns ns ns ns ns Mbps ns ns ns ns ns Mbps ns ns ns ns ns
Propagation Delay Skew1 Channel-Channel Skew Si843x-B Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL|
Propagation Delay Skew1 Channel-Channel Skew Si843x-C Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL|
Propagation Delay Skew1 Channel-Channel Skew
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Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = -40 to 125 C)
Parameter For All Models Output Rise Time Output Fall Time Common Mode Transient Immunity Enable to Data Valid Enable to Data Tri-State Start-up Time2
Symbol tr tf CTMI ten1 ten2 tSU
Test Condition CL = 15 pF See Figure 2 CL = 15 pF See Figure 2 VI = VDD or 0 V See Figure 1 See Figure 1
Min -- -- 25 -- -- --
Typ 2 2 30 5 5 3
Max -- -- -- -- -- --
Unit ns ns kV/s ns ns s
Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output.
ENABLE
OUTPUTS
ten1
ten2
Figure 1. ENABLE Timing Diagram
50% Typical Input
tPLH
90% 50% 90% 10%
tPHL
Typical Output
10%
tr
tf
Figure 2. Propagation Delay Timing
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Table 2. Electrical Characteristics
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = -40 to 125 C)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Enable Input High Current Enable Input Low Current SI8430/35-A,-B,-C, VDD1 SI8430/35-A,-B,-C, VDD2 SI8430/35-A,-B,-C, VDD1 SI8430/35-A,-B,-C, VDD2 Si8431-A,-B,-C, VDD1 Si8431-A,-B,-C, VDD2 Si8431-A,-B,-C, VDD1 Si8431-A,-B,-C, VDD2 SI8430/35-B,-C, VDD1 SI8430/35-B,-C, VDD2 Si8431-B,-C, VDD1 Si8431-B,-C, VDD2 SI8430-C, VDD1 SI8430-C, VDD2 Si8431-C, VDD1 Si8431-C, VDD2
Symbol VIH VIL VOH VOL IL IENH IENL
Test Condition
Min 2.0 --
Typ -- -- 3.1 0.2 -- 4 20 7 6 13 5 7 10 12 11 10 11 10 13 11 16 12 19
Max -- 0.8 -- 0.4 10 -- -- 10 9 17 8 11 15 18 16 14 16 15 18 15 20 18 25
Unit V V V V A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
loh = -4 mA lol = 4 mA VENx = VIH VENx = VIL All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC
VDD1,VDD2 - 0.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DC Supply Current (All inputs 0 V or at supply)
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
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Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = -40 to 125 C)
Parameter Si843x-A Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si843x-B Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si843x-C Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 -- -- -- -- 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 -- -- -- -- 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6.5 -- -- -- 1 1000 75 30 50 40 10 100 35 7.5 25 5 150 6.6 9.5 3 5.5 3 Mbps ns ns ns ns ns Mbps ns ns ns ns ns Mbps ns ns ns ns ns
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Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = -40 to 125 C)
Parameter For All Models Output Rise Time Output Fall Time Common Mode Transient Immunity Enable to Data Valid Enable to Data Tri-State Start-up Time
2
Symbol tr tf CTMI ten1 ten2 tSU
Test Condition CL = 15 pF See Figure 2 CL = 15 pF See Figure 2 VI = VDD or 0 V See Figure 1 See Figure 1
Min -- -- 25 -- -- --
Typ 2 2 30 5 5 3
Max -- -- -- -- -- --
Unit ns ns kV/s ns ns s
Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output.
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Table 3. Electrical Characteristics
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = -40 to 100 C)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Enable Input High Current Enable Input Low Current SI8430/35-A,-B,-C, VDD1 SI8430/35-A,-B,-C, VDD2 SI8430/35-A,-B,-C, VDD1 SI8430/35-A,-B,-C, VDD2 Si8431-A,-B,-C, VDD1 Si8431-A,-B,-C, VDD2 Si8431-A,-B,-C, VDD1 Si8431-A,-B,-C, VDD2 SI8430/35-B,-C, VDD1 SI8430/35-B,-C, VDD2 Si8431-B,-C, VDD1 Si8431-B,-C, VDD2 SI8430-C, VDD1 SI8430-C, VDD2 Si8431-C, VDD1 Si8431-C, VDD2
Symbol VIH VIL VOH VOL IL IENH IENL
Test Condition
Min 2.0 --
Typ -- -- 2.3 0.2 -- 4 20 6 5 11 5 7 9 11 9 9 8 9 10 10 12 12 15
Max -- 0.8 -- 0.4 10 -- -- 8 7 13 7 10 11 13 11 11 10 11 13 12 15 15 19
Unit V V V V A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
loh = -4 mA lol = 4 mA VENx = VIH VENx = VIL All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC
VDD1,VDD2 - 0.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DC Supply Current (All inputs 0 V or at supply)
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
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Table 3. Electrical Characteristics (Continued)
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = -40 to 100 C)
Parameter Si843x-A Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si843x-B Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si843x-C Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew
Symbol
Test Condition Timing Characteristics
Min
Typ
Max
Unit
0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 -- -- -- -- 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 -- -- -- -- 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 5 -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 -- -- --
1 1000 75 30 50 40 10 100 35 7.5 25 5 100 10 17 7 12 4
Mbps ns ns ns ns ns Mbps ns ns ns ns ns Mbps ns ns ns ns ns
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Table 3. Electrical Characteristics (Continued)
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = -40 to 100 C)
Parameter For All Models Output Rise Time Output Fall Time Common Mode Transient Immunity Enable to Data Valid Enable to Data Tri-State Start-up Time2
Symbol tr tf CTMI ten1 ten2 tSU
Test Condition CL = 15 pF See Figure 2 CL = 15 pF See Figure 2 VI = VDD or 0 V See Figure 1 See Figure 1
Min -- -- 25 -- -- --
Typ 2 2 30 5 5 3
Max -- -- -- -- -- --
Unit ns ns kV/s ns ns s
Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output.
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Table 4. Absolute Maximum Ratings
Parameter Storage Temperature Operating Temperature Supply Voltage Input Voltage Output Voltage Output Current Drive Channel Lead Solder Temperature (10s) Maximum Isolation Voltage Symbol TSTG TA VDD1, VDD2 VI VO LO Min -65 -40 -0.5 -0.5 -0.5 -- -- -- Typ -- -- -- -- -- -- -- -- Max 150 125 6 VDD + 0.5 VDD + 0.5 10 260 4000 Unit C C V V V mA C VDC
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet.
Table 5. Recommended Operating Conditions
Parameter Ambient Operating Temperature* Supply Voltage Symbol TA VDD1 VDD2 Test Condition 100 Mbps, 15 pF, 5 V 150 Mbps, 15 pF, 5 V Min -40 0 2.375 2.375 Typ 25 25 -- -- Max 125 100 5.5 5.5 Unit C C V V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage.
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Table 6. Regulatory Information
CSA The Si84xx is certified under CSA Component Acceptance Notice. For more details, see File 232873. VDE The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. UL The Si84xx is certified under UL1577 component recognition program to provide basic insulation to 2500 VRMS (1 minute). It is production tested > 3000 VRMS for 1 second. For more details, see File E257455.
Table 7. Insulation and Safety-related Specifications
Parameter Minimum Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Resistance (Input-Output)1 Capacitance (Input-Output) Input Capacitance2
1
Symbol L(IO1) L(IO2)
Test Condition
Value 7.7 min 8.1 0.008 min
Unit mm mm mm V pF pF
CTI RIO CIO CI
DIN IEC 60112/VDE 0303 Part 1
>175 1012
f = 1 MHz
1.4 4.0
Notes: 1. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1-8 are shorted together to form the first terminal and pins 9-16 are shorted together to form the second terminal. The parameters are then measured between these two terminals. 2. Measured from input pin to ground.
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Table 8. IEC 60664-1 (VDE 0884 Part 2) Ratings
Parameter Basic isolation group Test Conditions Material Group Rated Mains Voltages < 150 VRMS Installation Classification Rated Mains Voltages < 300 VRMS Rated Mains Voltages < 400 VRMS Specification IIIa I-IV I-III I-II
Table 9. IEC 60747-5-2 Insulation Characteristics*
Parameter Maximum Working Insulation Voltage Symbol VIORM Method a After Environmental Tests Subgroup 1 (VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC) Input to Output Test Voltage VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) After Input and/or Safety Test Subgroup 2/3 (VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC) Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V RS VTR Test Condition Characteristic 560 Unit V peak
896
1050
V peak
672 4000 2 >109 V peak
*Note: This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of 40/125/21.
Table 10. IEC Safety Limiting Values
Parameter Case Temperature Safety input, output, or supply current Symbol TS IS JA = 107 C/W, VI = 5.5 V, TJ = 150 C, TA = 25 C Test Condition Min -- -- Typ
--
Max 150 210
Unit C mA
--
*Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 3.
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Table 11. Thermal Characteristics
Parameter IC Junction-to-Case Thermal Resistance IC Junction-to-Air Thermal Resistance Device Power Dissipation* Symbol JC JA PD Test Condition Thermocouple located at center of package Min -- -- -- Typ 45 107 -- Max -- -- 250 Unit C/W C/W mW
*Note: The SI8430-C-IS is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 C, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
Safety-Limiting Current (mA)
200
110 125 130
175 162 150 125 100 75 50 25 0 0 50
2.75 V 5.5 V 3.6 V
100
150
200
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2
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2. Typical Performance Characteristics
15 13 Current (mA) 11 9 7 5 0 10 20 30 40 50 60 70 80 90 100 Data Rate (Mbps) 2.5V 5V 3.3V
19 17 Current (mA) 15 13 11 9 7 5 0 10 20 30 40 50 60 70 80
5V 3.3V
2.5V
90
100
Data Rate (Mbps)
Figure 4. SI8430/35 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation
25 5V 20 Current (mA) 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 Data Rate (Mbps) 3.3V 2.5V
Figure 6. Si8431 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation
19 17 Current (mA) 15 13 11 9 7 5 0 10 20 30 40 50 60 70
5V 3.3V
2.5V
80
90
100
Data Rate (Mbps)
Figure 5. SI8430/35 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load)
Figure 7. Si8431 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load)
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10 9 Delay (ns) 8 Falling Edge 7 6 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Rising Edge
Figure 8. Propagation Delay vs. Temperature 5 V Operation
10 9 Delay (ns) 8 7 6 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Falling Edge Rising Edge
Figure 9. Propagation Delay vs. Temperature 3.3 V Operation
15 13 Delay (ns) 11 9 7 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Falling Edge Rising Edge
Figure 10. Propagation Delay vs. Temperature 2.5 V Operation
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3. Application Information
3.1. Theory of Operation
The operation of an SI8430 channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single SI8430 channel is shown in Figure 11. A channel consists of an RF transmitter and receiver separated by a transformer. Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying and applies the resulting waveform to the primary of the transformer. The receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver.
TRANSMITTER
RF OSCILLATOR
RECEIVER
A
MODULATOR
DEMODULATOR
B
Figure 11. Simplified Channel Diagram
3.2. Eye Diagram
Figure 12 illustrates an eye-diagram taken on an SI8430. The test used an Anritsu (MP1763C) Pulse Pattern Generator for the data source. The output of the generator's clock and data from an SI8430 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that very low pulse width distortion and very little jitter were exhibited.
Figure 12. Eye Diagram
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4. Layout Recommendations
Dielectric isolation is a set of specifications produced by the safety regulatory agencies from around the world that describes the physical construction of electrical equipment that derives power from a high-voltage power system such as 100-240 VAC systems or industrial power systems. The dielectric test (or HIPOT test) given in the safety specifications places a very high voltage between the input power pins of a product and the user circuits and the user touchable surfaces of the product. For the IEC relating to products deriving their power from the 220-240 V power grids, the test voltage is 2500 VAC (or 3750 VDC--the peak equivalent voltage). There are two terms described in the safety specifications: Creepage--the distance along the insulating surface an arc may travel. Clearance--the distance through the shortest path through air that an arc may travel. Figure 13 illustrates the accepted method of providing the proper creepage distance along the surface. For a 220-240 V application, this distance is 8 mm and the wide body SOIC package must be used. There must be no copper traces within this 8 mm exclusion area, and the surface should have a conformal coating such as solder resist. The digital isolator chip must straddle this exclusion area.
Figure 13. Creepage Distance
4.1. Supply Bypass
The Si843x requires a 0.1 F bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed as close as possible to the package.
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4.2. Input and Output Characteristics
The Si843x inputs and outputs are standard CMOS drivers/receivers. The Si844x inputs and outputs are standard CMOS drivers/receivers. Table 12 details powered and unpowered operation of the Si84xx.
Table 12. Si84xx Operation Table
VI Input1,2 H L X X EN Input1,2,3,4 H or NC H or NC L H or NC VDDI State1,5,6 P P P UP VDDO State1,5,6 P P P P VO Output1,2 H L Hi-Z L Disabled Upon the transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 s. Disabled Upon the transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 s, if EN is in either the H or NC state. Enabled, normal operation. Comments
X X
L X
UP P
P UP
Hi-Z L
Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the enable control input located on the same output side. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si84xx is operating in noisy environments. 4. No Connect (NC) replaces EN1 on SI8430/35. No Connect replaces EN2 on the Si8435. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND. 5. "Powered" state (P) is defined as 2.375 V < VDD < 5.5 V. 6. "Unpowered" state (UP) is defined as VDD = 0 V.
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4.3. Enable (EN1, EN2) Inputs
Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic operation is summarized for each isolator product in Table 13. These inputs are internally pulled-up to local VDD by a 9 A current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si84xx is operating in a noisy environment.
Table 13. Enable Input Truth Table
P/N SI8430 EN1* -- -- Si8431 H L X X Si8435 -- EN2* H L X X H L -- Outputs B1, B2, B3 are enabled. Outputs B1, B2, B3 are disabled and in high impedance state. Output A3 enabled. Output A3 disabled and in high impedance state. Outputs B1, B2 are enabled. Outputs B1, B2 are disabled and in high impedance state. Outputs B1, B2, B3 are enabled. Operation
*Note: X = not applicable; H = Logic High; L = Logic Low.
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4.4. RF Radiated Emissions
The SI8430 family uses a RF carrier frequency of approximately 2.1 GHz. This will result in a small amount of radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but due to a small amount of RF energy driving the isolated ground planes which can act as a dipole antenna. The unshielded SI8430 evaluation board passes FCC requirements. Table 14 shows measured emissions compared to FCC requirements. Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less efficient antenna.
Table 14. Radiated Emissions
Frequency (GHz) 2.094 2.168 4.210 4.337 6.315 6.505 8.672 Measured (dBV/m) 70.0 68.3 61.9 60.7 58.3 60.7 45.6 FCC Spec (dBV/m) 74.0 74.0 74.0 74.0 74.0 74.0 74.0 Compared to Spec (dB) -4.0 -5.7 -12.1 -13.3 -15.7 -13.3 -28.4
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4.5. RF Immunity and Common Mode Transient Immunity
The SI8430 family has very high common mode transient immunity while transmitting data. This is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements show no failures up to 30 kV/s. During a high surge event the output may glitch low for up to 20-30 ns, but the output corrects immediately after the surge event. The Si843x family passes the industrial requirements of CISPR24 for RF immunity of 3 V/m using an unshielded evaluation board. As shown in Figure 14, the isolated ground planes form a parasitic dipole antenna, while Figure 15 shows the RMS common mode voltage versus frequency above which the Si843x becomes susceptible to data corruption. To avoid compromising data, care must be taken to keep RF common-mode voltage below the envelope specified in Figure 15. The PCB should be laid-out to not act as an efficient antenna for the RF frequency of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal enclosure, or otherwise shielded.
GND1
Isolator
GND2
Dipole Antenna
Figure 14. Dipole Antenna
5 RMS Voltage (V) 4 3 2 1 0 500
1000 Frequency (MHz)
1500
2000
Figure 15. RMS Common Mode Voltage vs. Frequency
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5. Pin Descriptions
VDD1 GND1 A1 A2 A3 NC EN1/NC GND1
1 2 3 4 5 6 7 8
Top View
16 15 14 13 12 11 10 9
VDD2 GND2 B1 B2 B3 NC EN2/NC GND2
Wide Body SOIC
Name VDD1 GND1 A1 A2 A3 NC EN1/NC* GND1 GND2 EN2/NC* NC B3 B2 B1 GND2 VDD2 SOIC-16 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type Supply Ground Digital Input Digital Input Digital I/O NA Digital Input Ground Ground Digital Input NA Digital I/O Digital Output Digital Output Ground Supply Description Side 1 power supply. Side 1 ground. Side 1 digital input. Side 1 digital input. Side 1 digital input or output. No Connect. Side 1 active high enable. NC on SI8430/35 Side 1 ground. Side 2 ground. Side 2 active high enable. NC on Si8435. No Connect. Side 2 digital input or output. Side 2 digital output. Side 2 digital output. Side 2 ground. Side 2 power supply.
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
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6. Ordering Guide
Ordering Part Number SI8430-A-IS SI8430-B-IS SI8430-C-IS Si8431-A-IS Si8431-B-IS Si8431-C-IS Si8435-B-IS Number of Inputs Number of Inputs VDD1 Side VDD2 Side 3 3 3 2 2 2 3 0 0 0 1 1 1 0 Maximum Data Rate 1 10 150 1 10 150 10 Temperature -40 to 125 C -40 to 125 C -40 to 125 C -40 to 125 C -40 to 125 C -40 to 125 C -40 to 125 C Package Type SOIC-16 SOIC-16 SOIC-16 SOIC-16 SOIC-16 SOIC-16 SOIC-16
Note: All packages are Pb-free and RoHS Compliant. Moisture sensitivity level is MSL2 with peak reflow temperature of 260 C according to the JEDEC industry standard classifications, and peak solder temperature.
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7. Package Outline: Wide Body SOIC
Figure 16 illustrates the package details for the Quad-Channel Digital Isolator. Table 14 lists the values for the dimensions shown in the illustration.
Figure 16. 16-Pin Wide Body SOIC Table 14. Package Diagram Dimensions
Millimeters Symbol A A1 D E E1 b c e h L Min -- 0.1 Max 2.65 0.3
10.3 BSC 10.3 BSC 7.5 BSC 0.31 0.20 0.25 0.4 0 0.51 0.33 0.75 1.27 7
1.27 BSC
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DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.11
Updated Table 7, "Regulatory Information," on page 14. Minor typographical edits.
Revision 0.11 to Revision 0.2
Updated Supply Current specifications in Table 1, "Electrical Characteristics," on page 4, Table 2, "Electrical Characteristics," on page 7, and Table 3, "Electrical Characteristics," on page 10. Updated performance plots in Figures 4, 5, 6, and 7. Added NC note (Note 3) to Table 10, "Si84xx Truth Table (Positive Logic)," on page 16. Added NC note (*) to "5. Pin Descriptions" on page 25.
Revision 0.2 to Revision 0.3
Updated Notes to Tables 1, 2, & 3. Updated Figure 2. Updated Tables 6-11 to clarify specifications, test limits, & device characteristics.
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NOTES:
Rev. 0.3
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CONTACT INFORMATION
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: PowerProducts@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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